Lib.rs

› Hardware support › RustHDL
#verilog #fpga #hardware

yanked rust-hdl-sim-chips

was by Samit Basu and 3 contributors

0.1.0 Oct 22, 2021

#75 in #verilog


Used in 2 crates

MIT and AGPL-3.0-only

61KB
1.5K SLoC

Chip simulations for testing in RustHDL

Dependencies

~6MB
~121K SLoC