17 releases (4 breaking)
new 0.5.0 | Nov 3, 2024 |
---|---|
0.3.0 | Oct 10, 2024 |
0.2.0 | May 11, 2024 |
0.1.9 | Mar 27, 2024 |
0.1.0 | Feb 19, 2023 |
#407 in Embedded development
623 downloads per month
Used in 2 crates
33KB
527 lines
qingke & qingke-rt
Low level access to WCH's QingKe RISC-V processors.
qingke-rt
This crate provides the runtime support for QingKe RISC-V processors.
This provides riscv
/riscv-rt
like functionality, with the following differences:
- Use vector table for interrupt handling
- Handle 1KB address alignment for the entry point(Qingke V2)
- In-SRAM code executing,
highcode
handling - PFIC support
- Conflicts with
riscv-rt
crate
Usage
#[qingke_rt::entry]
fn main() -> ! {
loop {}
}
// Or if you are using the embassy framework
#[embassy_executor::main(entry = "qingke_rt::entry")]
async fn main(spawner: Spawner) -> ! { ... }
#[qingke_rt::interrupt]
fn UART0() {
// ...
}
#[qingke_rt::highcode]
fn some_highcode_fn() {
// ...
// This fn will be loaded into the highcode(SRAM) section.
// This is required for BLE, recommended for interrupt handles.
}
Dependencies
~0.5–1MB
~23K SLoC