#risc-v #wch #low-level #ch32v

no-std qingke

Low level access to WCH's QingKe RISC-V processors

17 releases (4 breaking)

0.5.0 Nov 3, 2024
0.3.0 Oct 10, 2024
0.2.0 May 11, 2024
0.1.9 Mar 27, 2024
0.1.0 Feb 19, 2023

#508 in Embedded development

Download history 11/week @ 2024-08-01 18/week @ 2024-08-08 92/week @ 2024-08-29 66/week @ 2024-09-05 11/week @ 2024-09-12 37/week @ 2024-09-19 27/week @ 2024-09-26 27/week @ 2024-10-03 229/week @ 2024-10-10 154/week @ 2024-10-17 56/week @ 2024-10-24 478/week @ 2024-10-31 110/week @ 2024-11-07 301/week @ 2024-11-14

952 downloads per month
Used in 2 crates

MIT/Apache

33KB
527 lines

qingke & qingke-rt

Crates.io Crates.io docs.rs

Low level access to WCH's QingKe RISC-V processors.

qingke-rt

This crate provides the runtime support for QingKe RISC-V processors.

This provides riscv/riscv-rt like functionality, with the following differences:

  • Use vector table for interrupt handling
  • Handle 1KB address alignment for the entry point(Qingke V2)
  • In-SRAM code executing, highcode handling
  • PFIC support
  • Conflicts with riscv-rt crate

Usage

#[qingke_rt::entry]
fn main() -> ! {
    loop {}
}

// Or if you are using the embassy framework
#[embassy_executor::main(entry = "qingke_rt::entry")]
async fn main(spawner: Spawner) -> ! { ... }

#[qingke_rt::interrupt]
fn UART0() {
    // ...
}

#[qingke_rt::highcode]
fn some_highcode_fn() {
    // ...
    // This fn will be loaded into the highcode(SRAM) section.
    // This is required for BLE, recommended for interrupt handles.
}

Dependencies

~0.5–1MB
~22K SLoC