1 unstable release
0.1.0 | Aug 16, 2024 |
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#1336 in Hardware support
120KB
2.5K
SLoC
Netlist Verilog Parser
introduction
The verilog netlist parser is belong to iEDA project. The parser read netlist verilog file to eda tools.
dependence
The verilog netlist parser use pest crate to build syntax tree.
Dependencies
~2.1–4MB
~74K SLoC