#risc-v #vector #encode #rvv #command-line-tool

rvv-encode

Library to encode RISC-V V extension (rvv) instructions

14 releases

0.2.1 Jul 28, 2022
0.2.0 Jul 6, 2022
0.1.13 Apr 28, 2022
0.1.11 Feb 14, 2022
0.1.9 Jan 25, 2022

#16 in #riscv

35 downloads per month
Used in 2 crates

MIT license

145KB
3K SLoC

RVV encoder

  • rvv-encode - A Library to encode RISC-V V extension instruction
  • rvv-asm - A procedure macro to encode RISC-V V extension instructions
  • rvv-as - A command line tool to encode RISC-V V extension instructions

rvv-asm example

unsafe {
    rvv_asm::rvv_asm!(
        "vsetvl x5, s3, t6",
        "1: vle256.v v3, (a0), vm",
        "2:",
        "li {lo}, 4",
        lo = out(reg) lo,
    );
}

rvv-as usage

USAGE:
    rvv-as [OPTIONS] <ASM_FILE>

ARGS:
    <ASM_FILE>    The original assembly source file path

OPTIONS:
    -c, --comment-origin                     Use original instruction and its code as comment
    -p, --comment-prefix <COMMENT_PREFIX>    The comment prefix [default: #]
    -r, --reserved-only                      Only translate reserved rvv instructions

Dependencies

~2.2–3MB
~59K SLoC