Lib.rs

› Simulation | Development tools › Fayalite
#hdl #hardware #fpga #firrtl #semiconductor

fayalite-visit-gen

an implementation detail of fayalite -- Visit/Fold implementation generator

Owned by Jacob Lifshay, fayalite-hdl.

2 unstable releases

0.2.0 Oct 18, 2024
0.1.0 Jul 26, 2024

#29 in Simulation

Download history 106/week @ 2024-07-22 25/week @ 2024-07-29 2/week @ 2024-08-26 14/week @ 2024-09-16 11/week @ 2024-09-23 3/week @ 2024-09-30 1/week @ 2024-10-07 151/week @ 2024-10-14 13/week @ 2024-10-21 4/week @ 2024-10-28 8/week @ 2024-11-04

176 downloads per month
Used in fayalite

LGPL-3.0-or-later

36KB
963 lines

Fayalite

Fayalite is a library for designing digital hardware -- a hardware description language (HDL) embedded in the Rust programming language. Fayalite's semantics are based on FIRRTL as interpreted by LLVM CIRCT.

Dependencies

~1.7–2.7MB
~54K SLoC